?002 fairchild semiconductor corporation IRF720 rev. b IRF720 3.3a, 400v, 1.800 ohm, n-channel power mosfet this n-channel enhancement mode silicon gate power ?ld effect transistor is an advanced power mosfet designed, tested, and guaranteed to withstand a speci?d level of energy in the breakdown avalanche mode of operation. all of these power mosfets are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. these types can be operated directly from integrated circuits. formerly developmental type ta17404. features 3.3a, 400v ? ds(on) = 1.800 ? single pulse avalanche energy rated soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging jedec to-220ab ordering information part number package brand IRF720 to-220ab IRF720 note: when ordering, use the entire part number. g d s gate drain (flange) source drain data sheet january 2002
?002 fairchild semiconductor corporation IRF720 rev. b absolute maximum ratings t c = 25 o c, unless otherwise speci?d IRF720 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds 400 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 400 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d t c = 100 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 3.3 2.1 a a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 13 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 50 w linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 w/ o c single pulse avalanche energy rating (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as 190 mj operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v, (figure 10) 400 - - v gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 25 a v ds = 0.8 x rated bv dss , v gs = 0v, t j = 125 o c - - 250 a on-state drain current (note 2) i d(on) v ds > i d(on) x r ds(on)max , v gs = 10v (figure 7) 3.3 - - a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 1.8a, v gs = 10v, (figures 8, 9) - 1.5 1.8 ? forward transconductance (note 2) g fs v ds 10v, i d = 2.0a, (figure 12) 1.7 2.7 - s turn-on delay time t d(on) v dd = 200v, i d 3.3a, r gs = 18 ?, v gs = 10v, r l = 59 ? mosfet switching times are essentially independent of operating temperature -1015ns rise time t r -1421ns turn-off delay time t d(off) -3045ns fall time t f -1320ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 10v, i d = 3.3a, v ds = 0.8 x rated bv dss i g(ref) = 1.5ma, (figure 14) gate charge is essentially independent of operating temperature -1220nc gate to source charge q gs - 2.0 - nc gate to drain ?iller?charge q gd - 6.0 - nc input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz, (figure 10) - 360 - pf output capacitance c oss -55- pf reverse transfer capacitance c rss -20- pf internal drain inductance l d measured from the contact screw on tab to center of die modified mosfet symbol showing the internal device inductances - 3.5 - nh measured from the drain lead, 6mm (0.25in) from package to center of die - 4.5 - nh internal source inductance l s measured from the source lead, 6mm (0.25in) from header to source bonding pad - 7.5 - nh thermal resistance, junction to case r jc - - 2.5 o c/w thermal resistance, junction to ambient r ja free air operation - - 80 o c/w l s l d g d s IRF720
?002 fairchild semiconductor corporation IRF720 rev. b source to drain diode speci?ations parameter symbol test conditions min typ max units continuous source to drain current i sd modified mosfet symbol showing the integral reverse p-n junction rectifier - - 3.3 a pulse source to drain current (note 3) i sdm - - 13 a source to drain diode voltage (note 2) v sd t j = 25 o c, i sd = 3.3a, v gs = 0v, (figure 13) - - 1.6 v reverse recovery time t rr t j = 25 o c, i sd = 3.3a, di sd /dt = 100a/ s 120 - 600 ns reverse recovery charge q rr t j = 25 o c, i sd = 3.3a, di sd /dt = 100a/ s 0.64 - 3.0 c notes: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive rating: pulse width limited by maximum junction temperature. see transient thermal impedance curve (figure 3). 4. v dd = 50v, starting t j = 25 o c, l = 31 h, r gs = 25 ?, peak i as = 3.3a. typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. maximum transient thermal impedance g d s 0 50 100 150 0 t c , case temperature ( o c) power dissipation multiplier 0.2 0.4 0.6 0.8 1.0 1.2 2 1 0 25 50 75 100 125 150 4 i d , drain current (a) t c , case temperature ( o c) 5 3 t 1 , rectangular pulse duration (s) 10 z jc , transient thermal impedance ( o c/w) 10 -3 10 -2 0.1 1 10 -5 10 -4 1.0 0.01 0.1 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc + t c p dm t 1 t 2 single pulse 0.1 0.02 0.2 0.5 0.01 0.05 3.0 IRF720
?002 fairchild semiconductor corporation IRF720 rev. b figure 4. forward bias safe operating area figure 5. output characteristics figure 6. saturation characteristics figure 7. transfer characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature typical performance curves unless otherwise speci?d (continued) v ds , drain to source voltage (v) 10 0.1 10 1 i d , drain current (a) 100 10 2 dc 100 s 10 s 1ms 10ms 1 10 3 limited by r ds(on) area may be operation in this t j = max rated t c = 25 o c single pulse 0 1 0 40 80 120 200 2 3 i d , drain current (a) v ds , drain to source voltage (v) 4 160 5 v gs = 5.0v v gs = 6.0v v gs = 5.5v v gs = 4.5v v gs = 4.0v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max 0 1 0 3 69 15 2 3 i d , drain current (a) v ds , drain to source voltage (v) 4 12 5 v gs = 5.0v v gs = 10v v gs = 6.0v v gs = 5.5v v gs = 4.5v v gs = 4.0v pulse duration = 80 s duty cycle = 0.5% max 0 24 0.01 1 10 i d , drain current (a) v gs , gate to source voltage (v) t j = 150 o c t j = 25 o c 0.1 6810 pulse duration = 80 s duty cycle = 0.5% max v ds 50v 0 2 0 3 69 15 4 6 r ds(on) , drain to source i d , drain current (a) 8 12 10 on resistance v gs = 20v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max 3.0 2.4 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 r ds(on) , normalized on resistance t j , junction temperature ( o c) pulse duration = 80 s duty cycle = 0.5% max v gs = 10v, i d =1.8a IRF720
?002 fairchild semiconductor corporation IRF720 rev. b figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. transconductance vs drain current figure 13. source to drain diode voltage figure 14. gate to source voltage vs gate charge typical performance curves unless otherwise speci?d (continued) 1.25 1.15 1.05 0.95 0.85 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) i d = 250 a normalized drain to source breakdown voltage 1000 800 600 400 200 0 12 5102 5 10 2 c, capacitance (pf) v ds , drain to source voltage (v) c oss c rss c iss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gs i d , drain current (a) g fs , transconductance (s) 0 01 2 34 1 2 3 4 5 5 t j = 150 o c t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max 0 0.4 0.8 0.1 10 10 2 i sd , source to drain current (a) v sd , source to drain voltage (v) t j = 150 o c 1 1.2 1.6 2.0 t j = 25 o c pulse duration = 80 s duty cycle = 0.5% max q g , gate charge (nc) v gs , gate to source voltage (v) 0 0481216 4 8 12 20 v ds = 320v 20 16 i d = 3.3a v ds = 200v v ds = 80v IRF720
?002 fairchild semiconductor corporation IRF720 rev. b test circuits and waveforms figure 15. unclamped energy test circuit figure 16. unclamped energy waveforms figure 17. switching time test circuit figure 18. resistive switching waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 0.3 f 12v battery 50k ? v ds s dut d g i g(ref) 0 (isolated v ds 0.2 f current regulator i d current sampling i g current sampling supply) resistor resistor same type as dut q g(tot) q gd q gs v ds 0 v gs v dd i g(ref) 0 IRF720
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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